ECE 2300 - Digital Logic and Computer Organization

General Information

Introduction  to the design and implementation of practical digital circuits. Students start with boolean algebra and working up to a single-cycle microprocessor by the end or the semester. Labs are created using Altera Quartus and are written in Verilog. It is one of the three 2000 level classes required to major in ECE. (Crosslisted as ENGRD 2300).

Prerequisites

CS 1110 or CS 1112

Topics Covered

• Boolean logic
• State machines
• Combinational  and sequential digital logic
• Basic structure of ROM and RAM memories
• Single-cycle CPU
• Pipelined CPU
• Memory hierarchies
• Input/output systems

Workload

• The weekly problem sets are relatively easy
• The labs may take hours depending on how prepared you are and how quickly you can debug

Advice

• It is really helpful to have the prelabs fully tested and working before going into lab so you don't have to spend too much time in lab.
• In lab get a good, working breadboard and FPGA so you don't spend hours debugging. <-- One million times this. The odds of getting a bad FPGA aren't trivial at all, I got them in around a third of the labs.
• If you are working across computers (e.g. coding at home, deploying it on the lab computer, know that just copying the source files is enough, trying to copy entire projects leads to trouble. Always ask a TA about such problems, as Quartus seems to forget configurations and settings once in a while.
• Go to office hours. Someone has absolutely seen your bugs before.
• Be sure to learn verilog and some basic digital electronics BEFORE taking this course, as knowledge of verilog HDL and of elementary gates may be assumed (depending on the instructor) assumed even though none of the official prerequisites indicate so.

Past Offerings

Semester	Time	Professor	Median Grade
Spring 2014	TR 1:25-2:40	Zhiru Zhang	B+
Fall 2014	TR 11:40-12:55	Edward Suh	B+
Spring 2015	TR 1:25-2:40	Zhiru Zhang	?