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 General Information Edit

Dives into the topic of ASIC design and verification. The class focuses mainly on designing ASICs using the automated design methodology and will have students push their RTL designs through the ASIC flow. Students then analyze their designs quantitatively in terms of cycle time, energy, power, and area. The class is meant to serve as a continuation of ECE 4750.

Prerequisites Edit

ECE 4750

Topics Covered Edit

  • Hardware Description Languages
  • CMOS Devices
  • CMOS Circuits
  • Full-Custom Design Methodology
  • Automated Design Methodology
  • Packaging, Power Distribution, Clocking, And I/O
  • Testing and Verification
  • CMOS Combination Logic
  • CMOS Sequential State
  • CMOS Interconnect
  • Synthesis Algorithms
  • Physical Design Automatic Algorithms

Workload Edit

  • 1 Problem Set
  • 2 labs (All in Verilog or PyMTL)
    • Pipelined Integer Multiplier
    • Sorting Accelerator
  • 1 Midterm
  • Several Week Long Final Project
    • Milestone Report due each week
    • Project Demo to Prof. Batten
    • Final Report

Advice Edit

  • Severe. Be ready for a lot of work. The problem sets isn't extremely difficult, but was fairly time-consuming. The labs were not necessarily difficult but do take a lot of time. This is in part due to the fact that each design you create for a lab has to be pushed through the automated design flow, which can take 10-20 minutes per design iteration. Prof. Batten is a clear lecturer, but also talks fast, so make sure you're paying attention during the entire lecture.
  • The final project is fairly extensive and Prof. Batten expects a lot in terms of the weekly milestones and final reports. He is looking for near publishable quality in terms of writing and formatting. He is fairly helpful throughout the project though and is always willing to discuss ideas and potential implementations.

Past Offerings Edit

Semester Time Professor Median Grade
Spring 2019 TR 1:25 - 2:40 Christopher Batten Unknown
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